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71M6513/71M6513H
A Maxim Integrated Products Brand
V3P3
V3P3-10mV
V1
3 -Phase      Energy Meter IC
DATA SHEET
SEPTEMBER 2011
WDT dis-
abled
V3P3 -
400mV
Normal
operation,
WDT
enabled
when
VBIAS
(V1 < VBIAS)
the battery is
The MPU clock frequency is determined by the I/O RAM register MPU_DIV (0x2004[2:0]) and can be CE*2 MPU_DIV Hz
enabled
Battery or
reset
mode
0V
Figure 11: Voltage Range for V1
Internal Clocks and Clock Dividers
All internal clocks are based on the watch crystal frequency (CK32 = 32,768Hz) applied to the XIN and XOUT pins. The PLL
multiplies this frequency by 150 to 4.9152MHz. This frequency is supplied to the ADC, the FIR filter (CKFIR), the clock test
output pin (CKTEST), the CE DRAM and the clock generator. The clock generator provides two clocks, one for the MPU
(CKMPU) and one for the CE (CKCE).
-
where MPU_DIV varies from 0 to 7 ( MPU_DIV is 0 on power-up). This makes the MPU clock scalable from 4.9152MHz down
to 38.4kHz.
The circuit also generates a 2x MPU clock for use by the emulator. This clock is not generated when the I/O RAM register
ECK_DIS (0x2005[5]) is asserted by the MPU.
I2C Interface (EEPROM)
A dedicated 2-pin serial interface implements an I2C driver that can be used to communicate with external EEPROM devices.
The interface can be multiplexed onto the DIO pins DIO4 (SCK) and DIO5 (SDA) by setting the I/O RAM register DIO_EEX
(0x2008[4]). The MPU communicates with the interface through two SFR registers: EEDATA (0x9E) and EECTRL (0x9F). If the
MPU wishes to write a byte of data to EEPROM, it places the data in EEDATA and then writes the ‘Transmit’ code to EECTRL .
The write to EECTRL initiates the transmit sequence. By observing the BUSY bit in EECTRL the MPU can determine when the
transmit operation is finished (i.e. when the BUSY bit transitions from 1 to 0). INT5 is also asserted when BUSY falls. The MPU
can then check the RX_ACK bit to see if the EEPROM acknowledged the transmission.
A byte is read by writing the ‘Receive’ command to EECTRL and waiting for BUSY to fall. Upon completion, the received data
will appear in EEDATA .
The serial transmit and receive clock is 78kHz during each transmission, and SCL is held in a high state until the next
transmission. The bits in EECTRL are shown in Table 56.
The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly. However, controlling DIO4 and
DIO5 directly is discouraged, because it may tie up the MPU to the point where it may become too busy to process
interrupts .
? 2005-2011 Teridian Semiconductor Corporation
Page: 45 of 104
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